1. Field of the Invention
The present invention relates to hardware timers for processor-oriented systems, and more particularly to a scalable virtual timer architecture for efficiently implementing multiple hardware timers with minimal silicon overhead.
2. Description of the Related Art
As embedded applications become more complex, micrcontrollers have experienced a superintegration of memory and peripheral blocks, rendering chip resources even more valuable. The embedded applications industry has responded to superintegration with an effort to provide just enough silicon to microcontrollers to achieve the contemplated functionality. Implementation strategies for minimizing total silicon real estate while maintaining acceptable levels of performance are thus needed.
In large or protocol intensive applications for processor-oriented systems, numerous timers are used to provide reset functionality, interrupt generation functionality, event triggering functionality, and other timing functions. During the execution of these applications, a processor frequently checks the states of numerous timers. This polling of numerous timers has significantly contributed to software overhead in processor-oriented systems.
A basic hardware timer has included a counter, a set of registers, a comparator, and other circuitry (e.g., frequency scaling logic or control logic). A timer typically serves as a device for counting or timing events. A timer accomplishes such a purpose by accumulating (incrementing or decrementing) a count value until a programmed count value is reached. This counting operation is performed by a counter every certain number of clock transitions of a clock signal provided as an input to the timer. A counter, which is the core of a timer, has itself been referred to as a timer or counter/timer. When the timer reaches the programmed count value, the timer expires. Expiration of a timer is commonly termed a xe2x80x9ctime out.xe2x80x9d Following a time out, a timer generates a terminal count and performs or triggers a timer action which is typically providing an interrupt to a processor. A timer next may be cleared and reloaded with a new or same programmed count value.
A variety of registers may be used for controlling or supporting a timer. Examples of such registers include timer mode and control registers, timer count registers, load registers, and capture or hold registers. A timer mode and control register typically provides bits for enabling a timer, reflecting the state of a timer, arming a timer, controlling frequency prescaling of a timer, setting the type of timer action performed by a timer, setting a particular operating mode for a timer, and/or selecting a clock source for a timer. A timer count register contains a current count value of a timer. A load register is used to load a counter with a programmed count value. A capture or hold register is used to perform a capture or record operation whereby count data of interest such as the current count value is read by a device such as a processor.
A comparator of a timer is used in determining if the timer has reached its programmed count value. One implementation of such a comparator has been a timer max count compare register. A count compare register contains a programmed count value. For this implementation, the timer is configured to compare the timer max count compare register and a timer count register to determine if the timer has reached the programmed count value.
For processor-oriented systems supporting multiple hardware timers, a hardware timer frequently must provide counting and timing functions independent of any other hardware timer. A conventional approach to providing an additional hardware timer within a processor-oriented system has been to supply another counter, set of registers, comparator, and other circuitry.
The Am186(trademark) ED microcontroller is an example of a processor-oriented system supporting multiple hardware timers. The Am186(trademark) ED microcontroller supports three hardware timers, timer 0, timer 1, and timer 2. The timers are controlled by eleven 16-bit registers in the peripheral control block of the microcontroller. Timer 0 and timer 1 are each associated with a set of four 16-bit registers. The set includes a timer mode/control register, two timer max count compare registers, and a timer count register. The timer 2 is associated with a timer mode/control register, a timer max count compare, register, and a timer count register. Each supported timer of the microcontroller thus has its own set of registers.
Briefly, in accordance with the present invention, a scalable virtual timer system or subsystem and technique for efficiently implementing multiple hardware timers with minimal silicon overhead is provided.
One embodiment of the scalable virtual timer system includes a content addressable memory for storing an xe2x80x9cinitial statexe2x80x9d or count value of a free running counter and desired count durations for a plurality of virtual timers. When a sum of an xe2x80x9cinitial statexe2x80x9d of the free running counter and a desired count duration for a virtual timer of the plurality of virtual timers matches a state of the free running counter, the content addressable memory generates a terminal count for the virtual timer.
In an alternative embodiment of the scalable virtual timer system, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer of the plurality of virtual timers and the xe2x80x9cinitial statexe2x80x9d of the free running counter. A comparator of a plurality of comparators generates a terminal count for a virtual timer when a state of the free running counter matches a sum of an xe2x80x9cinitial statexe2x80x9d of the free running counter and the desired count duration for the particular virtual timer.
In accordance with the present invention, a technique for efficiently implementing multiple hardware timers with minimum silicon overhead utilizes the scalable virtual timer system. The state of the free running counter of the scalable virtual timer system is read. If the state of the free running counter matches a sum of an xe2x80x9cinitial statexe2x80x9d of the free running counter and a desired count duration stored in a storing means, then the particular match is detected. An operation for detecting such a match may involve adding the desired count duration and the xe2x80x9cinitial statexe2x80x9d of the free running counter. In response to detection of a match between the stored sum for a virtual timer and the state of the free running counter, the scalable virtual timer system generates a terminal count for the particular virtual timer.